Know about hardware

  The chief data paths within the ATM Camera V2 are shown in form. Analogue video from the connectors on the front panel is digitized immediately, either as separate luminescence and dominance channels (for the VHS case) or as a single PAL/SCENT composite signal. The digital sample stream is decoded by the Philips SAA7191 Digital Multi standard Decoder (Square Pixel) to produce a stream of 16-bit GUV pixels and all necessary horizontal and vertical sync signals. The decoder will routinely know PAL, SCENT or SEAM signal and adjust hence. The output of the decoder pass into the SAA7186 Digital Video Scalar chip which can take a specified rectangle of the input picture and scale it to any smaller size. In addition, it can perform a number of color-space conversion functions. Typically the productivity from the scalar chip is in the RGB color-space since this it what most frame-buffers require. Both the Decoder and Scalar are controlled by the Micro controller via an bus. The pixels from the scalar pass through an 24-bit wide DRAM large enough to hold 8 scan-lines of pixels. They are written into the DRAM in scan-line format and read out as 8x8 pixel tiles. At this point the data is written into video FIFO large sufficient to store an entire frame. This allows the capture of the pixel data to proceed completely decoupled from its transmission across the ATM network interface. The data from the FIFO may be transmitted as one of a number of uncompressed pixel formats by simple multiplexing of the bits, or may be passed through a JPEG compression engine (C-Cube CL550) to make a variable-bit-rate stream. A HI-PHI audio Codec provides audio samples at a number of rates, in delectable formats up to 48 kHz stereo 16 bit samples. The codec has 3 inputs and an output currently used for monitoring the capture channels. The Micro controller can also contract cells for transmission over the ATM interface using registers provided inside this Linux. This allows the MP to transmit synchronization streams etc. The bytes which result from all of these operations are marshaled into AAL5 Pd Us by a Xilinx 3190 GAFF. The cell assembly takes leave in a dual-ported DRAM. Another Linux on the other side of the DRAM manages the ATM interface and is responsible for setting up the length, CRC32 and the header ensign fields of each cell transmitted. This Xilinx supports four self-sufficient transmission channels: Raw video JPEG compressed video Audio Microelectronic IO Each channel is capable of multicasting to four destinations, although this feature is not currently used. Of the four channels, the MPU has right of way to avoid the state where control in sequence is unable to get through due to the high bandwidth requirement of the ATM video streams. On the AVA200 variant this Xilinx controls the two TAXI chips accountable for the ATM transmission interface. On the DAN variant the Xilinx presents the cell data directly to the switch fabric via two latches. ATM Rx is also supported by the transmission Xilinx which provides a method for the UMP to read the 9-bit wide Rx FIFO. The 9th bit is used to tag the start of each cell. The micro controller is intermittent when this FIFO is non-empty.